1. Field of the Invention
The invention relates generally to the field of design verification. More particularly, the invention relates to a new approach for functional verification of digital designs.
2. Description of the Related Art
The objective of design verification is to ensure that errors are absent from a design. Deep sub-micron integrated circuit (IC) manufacturing technology is enabling IC designers to put millions of transistors on a single IC. Following Moore's law, design complexity is doubling every 12-18 months, which causes design verification complexity to increase at an exponential rate. In addition, competitive pressures are putting increased demands on reducing time to market. The combination of these forces has caused an ever worsening “verification crisis”.
Today's design flow starts with a specification for the design. The designer then implements the design in a language model, typically Hardware Description Language (HDL). This model is typically verified to discover incorrect input/output (I/O) behavior via a stimulus in expected results out paradigm at the top level of the design.
By far the most popular method of functional verification today, simulation-based functional verification, is widely used within the digital design industry as a method for finding defects within designs. A very wide variety of products are available in the market to support simulation-based verification methodologies. However, a fundamental problem with conventional simulation-based verification approaches is that they are vector and testbench limited.
Simulation-based verification is driven by a testbench that explicitly generates the vectors to achieve stimulus coverage and also implements the checking mechanism. Testbenches create a fundamental bottleneck in simulation-based functional verification. In order to verify a design hierarchy level, a testbench must be generated for it. This creates verification overhead for coding and debugging the testbench. Hence, a significant amount of expensive design and verification engineering resources are needed to produce results in a cumbersome and slow process.
Several methods have been attempted by Electronic Design Automation (EDA) companies today in order to address the shortcomings of simulation. However, none of these attempts address this fundamental limitation of the process. For example, simulation vendors have tried to meet the simulation throughput challenge by increasing the performance of hardware and software simulators thereby allowing designers to process a greater number of vectors in the same amount of simulation time. While this does increase stimulus coverage, the results are incremental. The technology is not keeping pace with the required growth rate and the verification processes are lagging in achieving the required stimulus coverage.
Formal verification is another class of tools that has entered the functional verification arena. These tools rely on mathematical analysis rather than simulation of the design. The strong selling point of formal verification is the fact that the results hold true for all possible input combinations to the design. However, in practice this high level of stimulus coverage has come at the cost of both error coverage and particularly usability. While some formal techniques are available, they are not widely used because they typically require the designer to know the details of how the tool works in order to operate it.
In addition to the above deficiencies, the conventional tools are limited in their capacity to handle complex hardware designs. Currently, hardware designs are analyzed monolithically. In other words, at any level of hierarchy in the design, all the modules that constitute the hierarchy are analyzed together. However, analyzing all the modules together may not be feasible in large designs due to the resulting computational complexity. Furthermore, the existing tools lack the ability to provide the verification process as the design evolves, i.e., in concurrence with the design process. For instance, simulation can be applied only after the first full-chip integration.
Therefore, a verification methodology is needed that can avoid computational complexity problems when analyzing complex hardware designs and can be applied concurrently with the design process.